1. Field of the Invention
The invention relates to storage cells used in particular in storage arrangements of digital data processing systems, whereby the storage cells are arranged in a matrix, so that each individual cell can be addressed via corresponding selection means, with binary data being written into or read from it.
2. Description of the Prior Art
Of the great variety of known storage cells, several essential embodiments which relate more closely to the storage cell in accordance with this invention will be identified hereinbelow.
In, for example, commonly assigned U.S. Pat. No. 3,643,235, a storage cell is disclosed which includes a directly cross-coupled, bipolar transistor flip-flop circuit, whose two collector load resistors are two identical active semiconductor devices acting as controllable current sources. The two active semiconductor devices form two complementary transistors with a common base to the flip-flop transistors. For writing and reading information, the emitters of two transistors of the same conductivity type, similar to the emitter-linked flip-flop transistors with common collectors, are connected to a bit line pair. The collectors and the base terminals of these transistors are connected to a common potential, the base terminals being connected to the collectors of the two flip-flop transistors. In comparison with other known storage cells, this known storage cell has a number of advantages, such as low space requirements because of its integrated design, low power constumption in the non-addressed state, high read-write speeds, simple monolithic layout plus simple wiring, few contacts, and, in addition, it can be readily produced and has a high yield and a high degree of reliability.
A modified version of this storage cell is disclosed in commonly assigned U.S. Pat. No. 3,815,106. In comparision with the former storage cell, this latter cell has characteristics which meet even more exacting requirements. It requires fewer metallic lines, so that as a result of the reduction of the difficulties caused by electromigration, a higher degree of reliability, a higher circuit and information density, and thus a higher degree of economy are obtained. An essential feature is that only one metallization layer is required, so that the manufacturing process is simplified, with the yield being increased and the cost being decreased. With this known storage cell the base of each flip-flop transistor is connected to the emitter of an associated complementary addressing transistor, whose collector and base are respectively connected to an associated bit line and an address line. During writing the complementary addressing transistors are inversely operated, injecting current into the base of the associated flip-flop transistor, thus leading to an increase in the write speed. By means of lateral layouts and by merging the zones of the individual semiconductor elements, which are connected to the same potential, the desired simple semiconductor structure is obtained. For this purpose the collector load resistors consist of transistors which are complementary to the flip-flop transistors and whose emitters, base and collectors are respectively connected to a first addressing line, a second addressing line and to the associated flip-flop transistor.
In connection with the further development of the storage cell disclosed in the above cited U.S. Pat. No. 3,643,235, a monolithically integrated storage cell is known which includes a directly cross-coupled bipolar transistor flip-flop circuit, whose two collector load resistors are again two identical transistors acting as controllable current sources and being complementary to the flip-flop transistors which with an emitter arranged in a common base and connected to a common supply voltage potential and collectors arranged laterally thereto are designed as lateral transistors. For the purpose of addressing, the word lines and the supply voltage feed are combined, and the two emitters of the flip-flop transistors are connected to one bit line each of a bit line pair. The storage cell thus designed and operated has improved characteristics in particular with regard to the addressing means required.
In the field of logical circuits with bipolar transistors considerable progress has been made during the past few years, which has attracted great attention on the part of the experts and which under the term Merged Transistor Logic (MTL) or Integrated Injection Logic (I.sup.2 L) has become widely known in technical literature. Attention is drawn, for example, to articles in the IEEE Journal of Solid-State Circuits, Vol. SC-7, No. 5, October 1972, pp. 340 to 346. Relevant U.S. Patents are, for example, U.S. Pat. Nos. 3,736,477 and 3,816,758. This injection logic concept is essentially based on inverting single- or multiple-collector transistors which by the direct injection of minority charge carriers inside the semiconductor body are fed close to their emitter-base junctions (order of magnitude one diffusion length). This bipolar logic concept provides very short switching times. In addition, it is suitable for the manufacture of extremely highly integrated, large-scale logical circuits with a great number of logical elements producible on a single semiconductor chip. For the manufacture of logical circuits in highly integrated technology, essentially three prerequisites have to be fulfilled. The basic circuits must be as simple and space-saving as possible, so that as great a number of them as possible can be arranged on a single semiconductor chip. In addition, the layout of the circuits must be such that an adequate speed does not lead to an excessive increase in the power dissipation on the semiconductor chip, which is tantamount to the requirement that the product of the factors delay time and power dissipation per logical function should be as small as possible. Finally, to obtain a good yield and thus for economical and also for technological reasons the manufacturing process required must be as simple and readily applicable as possible. The inverting logical circuits described are not only outstandingly suitable for the manufacture of logical circuits but they can also be advantageously used as a component for monolithically integrated storage cells, utilizing the fact that in the case of inverting logical circuits two stages each are required to obtain storage cells in the manner of flip-flop circuits. Thus, a storage cell includes two such basic circuits which are symmetrically designed and whereby the output of one basic circuit is connected to the input of the other circuit to fulfill the feedback condition. In this manner the necessary cross-coupling, as exists with conventional flip-flop circuits, is obtained. From the above cited U.S. Pat. No. 3,815,106, a storage cell is known which is made up of two of the logical circuits described and whereby the collector of the inverting transistor of one circuit is in each case cross-coupled with the base of the inverting transistor of the other circuit. The two inverting transistors, in their turn, are inversely operated, forming the actual flip-flop transistors or switching transistors. The complementary transistor of each basic circuit, which is connected via a separate line and via which the minority charge carriers are injected, serves as a load element for both switching transistors. For the purpose of addressing, i.e., for writing and reading the storage cell, the base of each switching transistor is additionally connected to the emitter of an associated additional addressing transistor which is also complementary and whose collector and base are respectively connected to an associated bit line and an address line. Thus, in addition to the injecting transistor forming the load element, an addressing transistor is required which in turn is formed by a lateral transistor structure.
By laterally arranging the two circuits forming a storage cell and by merging the zones connected to the same potential, the desired simple semiconductor structure is obtained. By means of this known storage cell a storage matrix can be produced in which the storage cells are arranged at least in two horizontal lines and in at least four vertical columns. A first vertical address line is associated with the first and the second columns, and a second vertical address line is associated with the third and fourth columns. Furthermore, a first horizontal address line is associated with the first line, and a second horizontal address line is associated with the second line. Finally, a first, a second and a third bit line pair is respectively associated with the first, the second and the third, and the fourth column. For this purpose each bit line pair extends preferably in a vertical direction between the associated columns. The bit lines are in each case connected to the collectors of the addressing transistors, the first address line is connected to the emitters of the transistors forming the load elements and the second address line is connected to the bases of the addressing transistors.
Commonly assigned U.S. application having Ser. No. 763,183, filed Jan. 27, 1977, now abandoned describes an improved I.sup.2 L storage cell requiring only four transistors, two metal bit lines and a buried layer for addressing.